Methods of testing a memory macro in a semiconductor memory device equipped with a memory macro generally include a DA (Direct Access) mode for directly testing a memory macro cell using an LSI tester, and a BIST (Built-In Self-Test) mode for testing a memory macro cell by relying upon a tester function, which is provided within the cell, without using an LSI tester. There is a demand that the access time of a memory macro cell can be measured using these test methods.
For example, Japanese Patent Kokai Application No. JP-P2001-332099A discloses a semiconductor integrated circuit device (see FIG. 10) in which a Design for Test circuit (DFT) of each DRAM macro cell (DRAM) is furnished with a function for selectively placing a test control signal TACC at a valid level at the time of a test operation for access evaluation. Each DRAM macro cell includes a memory control circuit CTL and a multiplexer MXL. In accordance with a clock signal CLKN serving as a start-up control signal of the macro cell, the memory control circuit CTL generates an internal control signal COLC having a prescribed time relationship with respect to the clock signal. The multiplexer MXL sends the internal control signal COLC to an output data latch OL as an output latch control signal OLC at the time of ordinary operation in which the test control signal TACC is placed at an invalid level, and sends an output latch control signal TOLC, which is for testing purposes and is supplied from an external test device TST, to the output data latch OL as the output latch control signal OLC at the time of the above-mentioned test operation in which the test control signal is placed at the valid level.
In JP-2001-P332099A, access time is measured using the clock signal CLKN and the output latch control signal TOLC for testing purposes. At the time of normal operation, the output data latch OL is controlled by the internal control signal COLC generated from the clock signal CLKN. At the time of the test operation, however, the output latch control signal TOLC for testing is caused to be input as is to the output data latch OL by the test control signal TACC generated from the clock signal CLKN. As a result, the output data latch OL determines the output data at the rising edge of the output latch control signal TOLC for testing purposes, and delivers this output data to a data output terminal DO. It is possible to evaluate access time when the test operation is performed by checking the normalcy of the data output delivered via the output data latch OL while changing the time relationship of the test output latch control signal TOLC relative to the clock signal CLKN. Access time mentioned here refers to the time from input of the clock signal CLK serving as the start-up control signal from the external test device TST to output of normal data from the data output terminal DO of the DRAM, namely the time from the rising edge of the clock signal CLKN to the rising edge of the output latch control signal TOLC for testing.
Further, Japanese Patent Kokai Application No. JP-A-9-166646 discloses a semiconductor device (see FIG. 11) having a self-test circuit for performing a prescribed logical operation in order to self-test a testable circuit (circuit-to-be-tested) 203. A test signal is applied to the testable circuit 203 by an input-signal generating circuit 201, and a test-result output signal is latched by a latch circuit 208 in response to a strobe input signal (strobe signal). The strobe signal has a period T identical with that of a clock signal supplied to a synchronizing clock input signal terminal. By changing a phase difference tθ, the strobe position is varied. An output signal sequence that is output from the latch circuit 208 is compressed by an output-signal compression circuit 205 in sync with the clock signal, after which the compressed signal and an expected-value signal from an output-signal expected-value generating circuit 206 are compared by a comparator 207. Dynamic pass/fail of the testable circuit 203 is determined via a judgment-value output signal terminal. Here the access time refers to the time from determination of an address signal of the testable circuit 203 (e.g., an SRAM) to read-out of a stored signal from the corresponding address.
Furthermore, a semiconductor memory device equipped with a memory macro of the kind illustrated in FIG. 12 is known. This semiconductor memory device is mounted on a prescribed board (not shown) of a computer system and has logic units LC1 to LC6 and a memory macro MM on a semiconductor substrate CHIP. The latter is provided with a test-mode-dedicated pin TDQ in addition to input and output pins (I/O pins) for input and output data signals. Further, the semiconductor substrate CHIP is provided with a test-mode-dedicated clock signal pin (TCLK pin) and a flag signal pin (TFOUT pin) corresponding to a pass/fail flag dedicated to the test mode. These pins serve as contact terminals for connecting to a tester at the time of a probe test relating to access evaluation.
The logic unit LC1 is a combination of a number of logic-gate cells. Input signals (inclusive of a clock signal CLK and address signal ADD) are applied to the logic unit LC1, and the applied input signals (inclusive of the clock signal CLK and address signal ADD) are output to the memory macro MM. The logic unit LC2 is a combination of a number of logic-gate cells. Input signals (inclusive of a clock signal TCLK and address signal TADD) for testing purposes are applied to the logic unit LC2, which adjusts a prescribed signal in the test input signals and outputs the test input signals to the memory macro MM. In a case where the power-supply voltages of the memory macro MM and logic unit LC2 differ, the logic unit LC2 uses a voltage-adjusting level-shift circuit. If it is necessary to shape the signal waveforms of the memory macro MM and logic unit LC2, then the logic unit LC2 uses a buffer circuit.
In the normal mode, the input signals from the logic unit LC1 are applied to the memory macro MM, which outputs data DQ to a logic unit LC3. More specifically, in the normal mode, when the input signals (inclusive of a clock signal CLK and address signal ADD) are applied to the memory macro MM in the normal mode, a controller CTL activates a memory array MARY based upon the input signals, reads data corresponding the address signal ADD out of a memory cell in the memory array MARY, and supplies data DOUT, which has been read out of the memory array MARY, to output unit DO. The data DQ, which is the result of adjusting the data DOUT in the output unit DO, is output to the logic unit LC3.
In a test mode such as a DA mode, on the other hand, the input signals for testing from the logic unit LC2 are input to the memory macro MM, in response to which the memory macro MM outputs data DQ to the logic unit LC3 and outputs test data TOUT and/or TOUT2 to the logic unit LC4 or logic unit LC5. More specifically, in the test mode, when the test input signals (inclusive of the clock signal TCLK and address signal TADD) are supplied to the memory macro MM, the controller CTL activates the memory array MARY based upon the test input signals, reads data corresponding to the address signal TADD out of a memory cell in the memory array MARY, and supplies the data DOUT, which has been read out of the memory array MARY, to the output unit DO and to a DFT (Design For Test) circuit. The data DQ, which is the result of adjusting the data DOUT in the output unit DO, is output to the logic unit LC3. The test data TOUT and/or TOUT2, which is the result of determining whether or not the data DOUT has passed a prescribed standard test, is output to the logic unit LC4 or logic unit LC5 by the DFT circuit.
Accordingly, the normal input signals and the test input signals are input to the controller CTL, and it is so arranged that the mode is switched over to the normal mode or test mode depending upon whether or not a test mode signal is present in the test input signals. Further, the memory macro MM is equipped with the DFT circuit as a testing circuit (DA-mode or BIST-mode circuit). The data DOUT read out of the memory array MARY is input to the DFT circuit, in response to which the DFT circuit compresses the data DOUT, determines whether or not the compressed data DOUT passes the prescribed standard test, outputs the test data TDQ to the exterior of the reference substrate CHIP via the logic unit LC4, and outputs a flag signal TFOUT corresponding to a pass/fail flag to the exterior of the semiconductor substrate CHIP via the logic unit LC5.
The logic unit LC3 is a combination of a number of logic-gate cells. The output signal (inclusive of data DQ) from the memory macro MM is input to the logic unit LC3, which responds by producing an output signal (inclusive of data DQ). The logic unit LC4 is a combination of a number of logic-gate cells. The test data TOUT from the memory macro MM (DFT circuit) is input to the logic unit LC4, which responds by outputting the adjusted data TDQ. The logic unit LC5 is a combination of a number of logic-gate cells. The test data TOUT2 from the memory macro MM (DFT circuit) is input to the logic unit LC5, which proceeds to output the adjusted flag signal TFOUT. In a case where the memory macro MM and logic units LC4, LC5 have different power-supply voltages, the logic units LC4 and LC5 use voltage-adjusting level-shift circuits. If it is necessary to shape the signal waveforms of the memory macro MM and logic units LC4, LC5, then the logic units LC4 and LC5 use buffer circuits. The logic unit LC6 is a cluster of logic circuits constituting a portion other than a portion relating to the memory macro MM. The logic unit LC6 includes a SRAM macro or ROM, PLL, etc.
The details of the memory macro MM shown in FIG. 12 are as illustrated in FIG. 13. In a case where the memory macro MM is one having a number (e.g., 256) of inputs and outputs, providing TDQ pins in a number equivalent to the number of DQ pins is impossible in view of a constraint on the number of pins of the semiconductor substrate CHIP. Accordingly, several (e.g., eight) of these pins are provided.
In the read-out operation in the normal mode, the clock signal CLK (or access signal) from outside the memory macro MM is input to the memory macro MM, and the data DQ is read out of the memory cell in the memory array MARY corresponding to the address signal that is input simultaneously. Data DQ0 to DQ255 is output from the DQ pins.
In the DA mode, the test-mode-dedicated clock signal TCLK is used instead of the clock signal CLK, and the test-mode-dedicated address signal TADD is used instead of the address signal ADD. In the read-out operation in the DA mode, a clock signal TCLK0 from the logic unit LC2 is input to the memory macro MM, and data is read out of the memory cell in the memory macro MM corresponding to the address signal TADD input simultaneously. The data is output to the eight TDQ pins. Usually, data DOUT0 to DOUT255 extracted from nodes of the wiring between the memory array MARY and the output unit DO is input to the DFT circuit. When the data DOUT0 to DOUT255 enters the DFT circuit, it is compressed to eight items of data TOUT10 to TOUT 17 by a first I/O compression circuit (see FIG. 14A). The test data TDQ, which is the result of determining whether the items of compressed data TOUT10 to TOUT 17 are identical or not, is output from each of the TDQ pins. If DOUT0 to DOUT255 are identical, i.e., if they agree, then “0” is output from each of the TDQ0 to TDQ7 pins, thereby indicating “pass”. If they are not identical, i.e., if they do not agree, then “1” is output from each of the TDQ0 to TDQ7 pins, thereby indicating “fail”. As a result, the compressed data TOUT10 to TOUT 17 is processed in units of the external input addresses. In the DA mode, therefore, not only pass/fail but also good/faulty addresses can be ascertained.
In relation to the BIST mode, the semiconductor substrate CHIP is provided with the dedicated TFOUT pin for the flag signal TFOUT corresponding to the pass/fail flag. In the BIST mode, the inputs from outside the memory macro MM are only the test-mode-dedicated clock signal TCLK and initialization signal; the address signal is generated internally. In the read-out operation in the BIST mode, the test-mode-dedicated clock signal TCLK0 is input, data TOUT10 to TOUT17 that is output to the TDQ pins is extracted and the data TOUT10 to TOUT17 is compressed to a single item of compressed data TOUT2 by a second I/O compression circuit (see FIG. 4B) based upon an internal clock delay signal ICLKD and initialization signal INIT. Whether or not the items of compressed data TOUT10 to TOUT 17 are identical or not is output from the TFOUT terminal as a pass/fail flag. If these items of data are identical, i.e., if they agree, then “0” is output from the TFOUT pin, thereby indicating “pass”. If these items of data are not identical, i.e., if they do not agree, then “1” is output from the TFOUT pin, thereby indicating “fail”. The compressed data TOUT10 to TOUT17 at the pins TDQ0 to TDQ7 is subjected to overwrite processing. Therefore, if agreement continues, “0”s continue to be output. When there is non-agreement, “1”s continue to be output. In other words, ascertaining a faulty address is impossible and all that can be ascertained is merely pass/fail of the memory macro MM. The internal clock delay signal ICLKD is a signal obtained by delaying the internal clock signal ICLK and is generated by an ICLKD initial stage (not shown) based upon the internal clock signal ICLK from the controller CTL (ICLK initial stage). Further, the initialization signal INIT is a signal that is in phase with the initialization signal included in the test input signals and is generated by an INIT initial stage (not shown) based upon the initialization signal included in the test input signals.